Current techniques for large scale production of integrated circuits start with a single large and flat semiconductor substrate. For conventional integrated circuits, this substrate, or "wafer," is a disc of single-crystal silicon, currently up to 200 mm in diameter. In the case of a conventional active matrix liquid crystal display (AMLCD) panel, the substrate is a thin layer of amorphous, polycrystalline, or single-crystal silicon on a transparent substrate. Both conventional integrated circuits and displays use multiple processes to locally change the properties of the semiconductor material. The local changes form electronic component structures and. interconnections between structures to create a complete integrated circuit. The conventional manufacturing technique uses a photographic process to sequentially expose patterns onto the wafer. The patterns define the localities on the wafer where properties are to be modified. This conventional method can be used to etch metals, insulators or semiconductor material; deposit metals, insulators, or semiconductor material; and locally dope these materials with impurities, to define the local structure of the wafer. The repeated coordinated exposure of the wafer to different patterns allows the conventional photographic process to define where each process will have effect. The conventional photographic process uses a light-sensitive masking material on the surface of the semiconductor substrate. In localized doping, for example, depending on the light sensitive masking material used, the part of the substrate surface which was either exposed or masked from light would receive a deposit of a chemical dopant. This photographic, or masking, process can be repeated, using various dopants, until the desired integrated circuit is formed. Each masking process is coordinated with the prior masking process to align the multiple layers of semiconductor material to form three dimensional electronic components and interconnections. This conventional technique has been successfully adapted to doping the semiconductor by ion implantation or diffusion, to etch the semiconductor, insulator, or conducting layers previously deposited on the substrate, and to selectively deposit new materials. After processing, the conventional semiconductor wafer is cut into individual integrated circuits.
As used in the prior art, the conventional masking or photographic process has certain limitations for the rapid manufacture of very large quantities of devices, and is a very expensive method of manufacturing small quantities of many different types of devices. In addition, the conventional process exposes wafers to possible contamination. First, the conventional photographic process requires the use of optical masks which must be custom-made for each type of device. Optical masks are expensive to make and once made can only produce one particular type of circuit. Second, the conventional processes are applied as a series of discrete process stages where single wafers must be moved from process to process. The handling of the wafers between process stages exposes the wafers to atmospheric contaminants and other possible damage and also consumes factory time. The interprocess transportation of wafers and unavoidable exposure to atmospheric contaminants is especially damaging to large semiconductor devices, such as AMLCDs.
The conventional photographic technique can be used to create structures on large surface area devices. However, to overcome optical limitations, some of the conventional masking processes only expose partial sections of the substrate surface. The partial exposure technique requires the different exposed sections be "stitched" or "stepped" together until the entire substrate surface is exposed. The partial exposure method requires special electronic and mechanical apparatus to assure that the stitching occurs with the required accuracy. While the conventional partial exposure technique can be used to fabricate large surface area semiconductors, the stitching process adds to the semiconductor production cost because it reduces manufacturing throughput. This method suffers from many of the same disadvantages as the conventional photographic process. The partial exposure process does not obviate the manual transportation of wafers between processing stages. As in the single conventional mask method, the interprocess transportation exposes the wafer to contaminants and possible damage.
There exist methods and apparatus, such as U.S. Pat. No. 4,728,406 to Arindam Banerjee, et al., issued on Mar. 1, 1988 to increase manufacturing throughput by continuously manufacturing high volumes of large area thin film solar cells by plasma deposition. Other bulk deposition methods and apparatus as taught in, U.S. Pat. No. 4,438,723 to Vincent D. Cannella, et al., issued Mar. 27, 1984; U.S. Pat. No. 4,485,125 to Masatsugu Izu et al., issued on Nov. 27, 1984; and U.S. Pat. No. 4,664,939 to Herbert Ovshinsky, issued May 12, 1987, exist that continuously manufacture large area thin film cells. Such techniques were developed to produce high volumes of solar cells. The methods disclosed are for continuously depositing semiconductor material onto a metal foil. These methods may be useful for the fabrication of supply material for the present invention and are herein incorporated by reference. Such methods, however, do not teach or suggest any method of continuous manufacture and formation of discrete electronic structures of the type required for DRAMS, MPUs, and AMLCDs.
There exists a method of fabricating polycrystalline silicon strips by depositing on the top face of a carbon ribbon a layer of silicon and burning away the carbon ribbon supporting the silicon layer immediately following deposition of the silicon. Such a method is disclosed in U.S. Pat. No. 4,478,880 to Christian Belouet, issued Oct. 23, 1984. This patent discloses a process to manufacture a continuous strip of silicon semiconductor substrate.
There exist methods, such as U.S. Pat. No. 4,681,654 to Calviello et al., issued Dec. 6, 1988, that disclose a continuous manufacturing process for semiconductor chip packaging. The disclosed method shows that integrated circuits can be packaged into plastic or ceramic "chip" packages using a continuous process.
There exist methods and apparatus, such as U.S. Pat. No. 4,227,291 to John C. Schumacher, issued Oct. 14, 1980, that disclose a process for continuous production of an elemental semiconductor matrix with a partial recovery of the energy expended in the production process. The method is used to manufacture solar cells and recover energy from the manufacturing process.
There exist systems, such as U.S. Pat. No. 5,256,562 to Duy-Phach Vu et al., issued Oct. 26, 1993, that disclose a discrete method for fabricating active matrix displays by using a thin film transfer process to remove tiles of circuits (formed in silicon thin films) and transferring, locating and adhering the removed tile to a common module body.
There exist systems, such as U.S. Pat. No. 4,789,645 to Calviello et al., issued Dec. 6, 1988, that disclose a discrete method of manufacturing monolithic microwave integrated circuits from the top down. This method discloses that a monolithic microwave circuit can be fabricated in the discrete steps of depositing semiconductor material and etching parts of the material to leave a useful structure as the remainder. The disclosed fabrication method uses conventional photographic techniques to form novel circuit structures.
There exist systems, such as U.S. Pat. No. 3,790,404 to Richard R. Garnache et al., issued on Feb. 5, 1974, for an apparatus for effecting uniform and continuous mass transport reactions, such as oxidation, diffusion and etching between gaseous phase reactants and semiconductor substrates. The disclosed apparatus is a longitudinal process tube with an entrance zone and exit zone that can be used to uniformly produce unprocessed semiconductor wafers.
There exist systems, such as U.S. Pat. No. 3,667,989 to J. M. Keating, issued on Jun. 6, 1972, that disclose a method for selectively coating a discrete transistor component while crudely masking the transistor flange in order for the packaging material to adhere to the flange and seal the transistor.
It is one objective of the present invention to overcome the throughput limitations of current manufacturing methods for integrated circuits, by replacing the sequential handling of single substrates or wafers by a continuous process with greater throughput.
It is a further objective of the present invention to replace separate processing machines with a single continuous-flow machine in which processes are performed sequentially to overcome the problem of production failures due to dust and other local contamination by reducing or eliminating the need to transport substrates-in-process between processing stations.
It is a further objective of the present invention to use a direct energy beam manufacturing method in conjunction with a continuous manufacturing process. These and other advantages of the instant invention will be apparent from the brief description, the drawings and the detailed description thereof which follow.